Industry

Industry — Memory Semiconductors

Memory chips are a commodity-like, three-player oligopoly that turns silicon wafers into the highest-volume programmable matter on earth. The mental model: a global market worth roughly $200B a year, dominated by three vertically integrated DRAM manufacturers (Samsung, SK hynix, Micron) and four-to-five NAND makers (Samsung, Kioxia, SanDisk, SK hynix/Solidigm, Micron), where each new generation of capacity costs tens of billions of dollars to build, prices swing 50–80% peak-to-trough in a normal cycle, and a single product family — High-Bandwidth Memory bonded to AI accelerators — is currently bending the profit pool toward whichever supplier ships first and yields best.

1. Industry in One Page

DRAM (volatile working memory used in servers, PCs, phones, and graphics cards) is a roughly $130B+ annualized market in 2025; NAND (non-volatile flash storage in SSDs, smartphones, and embedded devices) is roughly $60–70B. Together they were ~$171B globally in calendar 2025 per Fortune Business Insights, and DRAM revenue alone hit $41.4B in 3Q 2025 (TrendForce), the highest quarterly print on record.

The economics turn on three things investors usually misunderstand. First, almost all the cost is fixed: a leading-edge memory fab costs $15–25B to build, runs 24/7, and depreciates whether it sells a wafer or not — so suppliers cut price, not volume, in a downturn. Second, there are only three at-scale DRAM makers and four-to-five NAND makers, so each producer's capex decision moves industry supply 5–15%, and one producer over-investing crushes the price for everyone (FY2008, FY2012, FY2016, FY2023). Third, High-Bandwidth Memory (HBM) consumes about three times as many wafers as commodity DRAM to ship the same number of bits, which means scaling HBM cannibalizes standard DRAM supply and propagates price inflation across the entire portfolio. That is the dynamic Wall Street is calling the "AI memory supercycle."

The thing newcomers usually miss: memory is not a "tech" margin business in the SaaS sense. It is closer to a refining or paper business — capital-intensive, price-taking, with margins that swing from negative to 60%+ inside 18 months. The current AI-driven upcycle is the fattest profit window the industry has ever seen; the question for Micron is whether HBM has enough customer-specific qualification friction to make it more contract-like and less commodity-like than legacy DRAM.

2. How This Industry Makes Money

Revenue model: bits × ASP. Suppliers sell bits of memory (gigabits or gigabytes) at an average selling price (ASP) per gigabit. Every quarter, an analyst tracks two numbers: bit shipment growth and ASP change. Bit shipments grow ~15–20% per year structurally (more memory in every server, phone, and car). ASPs are set by the marginal supply/demand balance and can move 50%+ in either direction in a single quarter.

Cost structure: dominated by depreciation and process complexity. About 60–70% of cost of goods sold in good times is capital-related (depreciation, equipment, facilities). Cost reduction comes from process node migration: each new node packs more bits into the same wafer, lowering cost per bit by 15–25%. If a competitor migrates faster, you become the high-cost producer.

Pricing unit and contract structure. DRAM is sold on quarterly or even monthly contract pricing to large OEM and cloud customers, plus a smaller spot market. NAND is similar but more liquid. HBM, uniquely, is increasingly sold on multi-year supply agreements tied to specific GPU platforms (e.g., Micron's "fully committed 2026 capacity" and a five-year deal disclosed in Q2 FY2026). That shifts a slice of memory away from the spot/contract cycle toward something closer to a long-term OEM contract.

Bargaining power. Buyers (hyperscalers, Apple, Samsung Mobile) are concentrated and sophisticated, but in shortage they have nowhere else to go: Micron's CEO has publicly said memory makers expect to meet only "half to two-thirds of demand from several key customers" through 2026. Equipment suppliers (ASML in particular) and a handful of materials vendors hold structural pricing power across the cycle because they are sole or near-sole sources.

Capital intensity is the single most important number. Combined 2026 memory capex from Samsung memory + SK hynix + Micron is heading toward ~$70B — more than the entire NAND industry's annual revenue at trough pricing. The industry's long-run return on invested capital depends on whether bit demand absorbs that capex or whether it triggers the next downcycle.

3. Demand, Supply, and the Cycle

Memory cycles are the most violent in semis. Micron's own income statement is the simplest illustration: gross profit went from $13.9B in FY2022 to negative $1.4B in FY2023 — a $15B swing on a 50% revenue decline — and back to $14.9B in FY2025. Cycles compress to ~18 months in the current AI-driven era, versus ~3–4 years historically, because hyperscaler capex orders move much faster than the old PC/handset cycle ever did.

Where downturns hit first, in order: ASP, then gross margin, then operating cash flow, then bit shipments (because suppliers run hard to defend share), then book value as inventory is written down, then capex (after a lag of 6–12 months). The first numbers a careful reader watches are contract DRAM prices on TrendForce/DRAMeXchange feeds, not Micron's own reporting.

The defining feature of the current cycle is HBM-induced wafer cannibalization: every additional HBM cube takes wafer capacity that would have produced commodity DDR5/LPDDR5. TrendForce reported DRAM contract prices rising 45–50% QoQ heading into Q4 2025 with combined contract prices (DRAM + HBM) up 50–55%. Micron and SK hynix have publicly said HBM is sold out for 2026.

4. Competitive Structure

Memory is one of the most concentrated markets in technology. Three players make essentially all leading-edge DRAM. NAND is slightly more fragmented but still a four-to-five-firm market. The closest analog in the industrial economy is commercial aircraft (Airbus/Boeing) or large-bore mining equipment — high fixed cost, high entry barriers, scale-sensitive, with each player closely watching the others' capex announcements.

Three structural facts shape the whole industry. First, leading-edge memory has no commercially viable Western foundry alternative — there is no TSMC for memory. The chip you buy was made in Idaho, Singapore, Hiroshima, Icheon, Pyeongtaek, or one of a handful of Taiwanese sites; that is the entire global supply base. Second, government subsidies are competitor-grade actors. The U.S. CHIPS Act allocated up to $6.4B to Micron; the Chinese government has poured tens of billions into CXMT and YMTC, and Micron's products were banned from Chinese critical-information-infrastructure operators in May 2023 — a decision that still shapes its addressable market. Third, Korean conglomerates carry the largest cycle ammunition: Samsung's chaebol structure and SK hynix's investment-grade balance sheet have historically let them sustain capex through downturns when Micron has had to cut.

5. Regulation, Technology, and Rules of the Game

Memory is one of the most politically exposed industries in technology because every advanced economy now treats semiconductor manufacturing as critical infrastructure.

The technology layer matters as much as the regulatory one. EUV lithography (only available from ASML) is the gating technology for sub-10nm DRAM nodes; whichever memory maker integrates EUV first gets a 12–18 month cost-per-bit advantage. Hybrid bonding for HBM eliminates solder bumps between stacked dies, cutting thermal resistance and enabling 12+ layer stacks; Micron has built a 621-patent portfolio around hybrid bonding versus SK hynix's 315 (per Forbes/Trefis), which the company is leveraging into the HBM4 generation. 3D NAND layer counts (currently moving from 200-layer "G8" to 300-layer "G9" generations) are the equivalent metric for flash. Standards bodies (JEDEC) set interfaces; first-to-volume on a new standard captures the early-cycle premium.

6. The Metrics Professionals Watch

Most beginner-friendly ratios — P/E, EPS, dividend yield — are nearly useless in memory because the denominator swings 10x across the cycle. The metrics below are the ones a memory desk actually uses.

The two metrics that most often drive thesis-changing surprises are (1) HBM mix, because each percentage point shifts blended ASP measurably and locks in a longer-duration revenue stream, and (2) inventory days at hyperscalers, because a single quarter of cloud digestion can flip the cycle. Pure financial ratios (P/E, ROE) are outputs of these two; relying on them as inputs is how investors get caught long at peak.

7. Where Micron Technology, Inc. Fits

Micron is the #3 DRAM, #5 NAND, and #2 HBM producer in the world — a scale player with a credible technology lead in selected nodes, but a pure-play exposed to the cycle without the diversified-conglomerate cushion that Samsung has and without the platform-share durability SK hynix has built at NVIDIA. It is the only U.S.-headquartered memory manufacturer of meaningful scale, which gives it a unique geopolitical dimension Korean and Chinese peers do not carry.

What this means for the rest of the report. The reader should not evaluate Micron primarily as a "tech stock." It is a high-fixed-cost, oligopolistic commodity producer with a mid-cycle ROIC that historically struggles to beat its cost of capital but can post extraordinary peak-cycle returns. The investment debate is therefore not "is the company good" but "where are we in the cycle, how much HBM mix is durable, and how much of a Chinese-substitution and oversupply discount is appropriate."

8. What to Watch First