Industry

Memory Semiconductors — The Arena Micron Plays In

Memory is the part of the semiconductor world that sells bits, not chips. A handful of companies make DRAM (volatile working memory) and NAND (non-volatile storage), the customers are hyperscale cloud, PC, smartphone, and automotive OEMs, and pricing is set by the global supply-demand balance of bits per quarter. It is the most capital-intensive, most cyclical, and most concentrated corner of semis: three firms control roughly 90% of DRAM revenue and four firms over 90% of NAND, every player runs at $15–30B of annual capex, and gross margins routinely swing from negative 9% to plus 60% within a five-year window. The newcomer's mistake is to think of memory as a "tech" business — it is closer to a global commodity producer with a Moore's Law cost curve and a strategic-asset overlay since AI changed who buys the bits and why.

1. Industry in One Page

The big idea. Memory has three permanent realities. (1) The cost of one bit falls about 15–20% per year because of process shrinks — so revenue per bit must fall too, and only the lowest-cost producer survives a downturn. (2) Demand is cyclical and inventoried; when AI accelerators or smartphones overbuild, the industry overbuilds with them and prices collapse 30–60%. (3) The industry is too concentrated to be a true commodity — three DRAM makers (Samsung, SK hynix, Micron) coordinate cadence implicitly via capex discipline, which is why the 2024–2026 AI tightness has lasted longer than past upcycles. AI changed the demand mix more than the level: a single Nvidia Rubin Ultra module needs 512 GB of HBM vs. 80 GB on an H100, and each HBM bit consumes roughly 3× the wafer area of standard DDR5. That "die penalty" silently tightens the rest of DRAM.

2. How This Industry Makes Money

Unit of sale: the bit. Memory revenue is bit shipments × average selling price per bit. Bit shipments grow about 15–25% per year long-term as customers absorb more content; ASP per bit falls structurally. Whether revenue grows or shrinks in any given year depends entirely on whether ASP declines exceed bit growth.

Cost structure. A 300mm memory wafer carries roughly 70% fixed cost — depreciation on a fab that cost $15–25B to build, EUV lithography tools at $200M each, plus skilled labor and utilities. Variable cost (silicon wafer, chemicals, gases) is small. The implication is brutal: fabs must run near full utilization or they bleed cash on the depreciation, and any underutilization charge flows straight to gross margin. In FY2023 Micron's underutilization charge and inventory write-downs together pushed gross margin to negative 9% even though revenue was only down a third. Capital intensity runs 30–50% of revenue at the leaders — Micron's FY2025 capex of $15.9B on $37.4B of revenue (42%) is typical, and FY2026 guidance is above $25B.

Where bargaining power sits. Three places. First, EUV lithography, where ASML is the sole supplier of leading-edge tools and Micron is its newest large customer (1γ DRAM in FY2025 is Micron's first EUV node). Second, advanced packaging, where TSMC CoWoS and HBM TSV stacking are bottlenecks shared by all three memory makers and a handful of AI accelerator customers. Third, NVIDIA qualification, which gates which HBM supplier ships into the highest-margin AI parts. Memory buyers themselves have only situational power — when supply is loose, hyperscalers force long-term price-down agreements; when it is tight, as in 2025–2026, Micron has sold out HBM capacity for the year and is signing first-ever five-year HBM supply agreements with volume and pricing commitments.

3. Demand, Supply, and the Cycle

Downturns are written into the historical record

Where the cycle hits first. ASPs move first, in the spot market. Then inventory days spike at memory makers as cancellations flow through. Then gross margin collapses, often with non-cash write-downs of finished inventory to net realisable value (FY2023 was $1.8B for Micron). Operating cash flow compresses, capex is cut, equipment orders are delayed at ASML and AMAT, and labour is reduced (Micron cut 10% of headcount in FY2023). The reverse is symmetric: when prices firm, HBM and high-capacity DIMM mix shifts up first, then standard-DRAM pricing follows as HBM consumes wafer capacity, then NAND lags by one to two quarters. AI is doing something genuinely new — HBM is sold under long-term agreements rather than spot, which should dampen high-frequency price swings. But every major supplier is guiding capex above $20B for CY2026, which historically has produced oversupply within 2–3 years.

4. Competitive Structure

DRAM is a three-firm oligopoly. NAND is a four-firm oligopoly. HBM (the AI sub-segment of DRAM) is effectively a three-firm race in which the qualification timeline at NVIDIA determines who captures each new generation.

Why concentration matters. Memory consolidation went from ~10 DRAM makers in 2008 to three by 2014 — a process Micron drove with the Elpida (2013) and Inotera (2016) acquisitions. The three survivors now coordinate capex implicitly: when one cuts production or guides capex down, the others tend to follow. In late 2023, Samsung — historically the most aggressive — for the first time cut output to support pricing alongside SK hynix and Micron. That oligopoly discipline is the difference between a 6-quarter and a 12-quarter recovery. The structural risk to this discipline is China: CXMT (DRAM) and YMTC (NAND) are state-backed, run on subsidised capital, and the May 2023 CAC decision banning Micron sales to Chinese critical-info infrastructure operators is the political-economy mirror image of that competitive pressure.

5. Regulation, Technology, and Rules of the Game

Why the policy layer matters for valuation. Memory used to be a pure cost-curve race. Today it has a strategic-asset overlay: a third of Micron's planned US capex is supported by government grants and tax credits, foreign supply is tariff- and export-control-exposed, and the tax rate is set by Singapore-Pillar-Two-OBBBA interactions rather than statutory federal alone. None of this changes the underlying physics of bits per wafer, but it changes which producer captures the marginal margin dollar.

6. The Metrics Professionals Watch

Industry-defining KPIs sit in a small set that the major banks track quarter by quarter. Standard ratios (P/E, ROE) miss the cycle; these don't.

7. Where Micron Technology, Inc. Fits

Micron is the only US-listed scale producer in DRAM and the only US-headquartered top-three memory maker globally. It is not a niche player and not a logic-design house: it is a pure-play, vertically integrated manufacturer that competes on process-node leadership, capital intensity, and customer qualification. Where the rest of the report digs into the company-specific strategy, valuation, and balance sheet, the industry framing places Micron as follows.

The CMBU operating margin at 45% is the single most important number on this page: it is roughly triple the consumer-segment margin and explains why HBM mix shift is the dominant cyclical driver of Micron's earnings power in the current cycle. It also explains why a slowdown in hyperscaler AI capex — not a PC or smartphone slowdown — is the largest single tail risk in the industry view.

8. What to Watch First

Seven observable signals that will tell a reader whether the industry backdrop is improving or deteriorating for Micron, in order of how quickly they move.